Technological Field
The present disclosure is related to a method for producing a stack of semiconductor devices by reflowing a solder material and the stack of semiconductor devices obtained by such a method.
Description of the Related Technology
3D semiconductor packaging technology stacked devices are used to reduce footprint and volume, as well as power consumption due to shorter interconnections. Typically thinned semiconductors are used in 3D bonding to reduce the height of the stack, which allows the use of Through Substrate Via (TSV) in multiple die stacking. “High Density Cu—Sn TLP Bonding for 3D Integration” by Rahul Agarwal, Wneqi Zhang, Paresh Limaye and Wouter Ruythooren from IMEC vzw, IEEE Paper 978-1-4244-4476-2/09 (June 2009), discloses a Cu/Sn/Cu bonding technique with a Transient Liquid Phase thermo-compression bonding technique, using a Cu UBM landing substrate and a Cu UBM with Sn Bump on the die substrate. During the TLP a solder Flux or Non-flow Under Fill (NUF) is required. The alignment accuracy is limited by the pick and place equipment, which in return limits further downscaling of the interconnects. Due to handling and BEOL reliability reasons, the pressure used during the bonding process becomes critical as scaling dictates that also the thickness of the devices to be stacked is further reduced to allow high count stacks using TSV. There is thus a need for an improved bonding process that allows thinner devices with smaller pitches for the bonding interconnect between the devices in the stack, while maintaining the low temperature of the bonding process.